Why do RMWs require flushing of write buffer in TSO?
I have been reading "A Primer on Memory Consistency and Cache Coherence" to understand more about how cache coherence is involved in atomic operations.I am a bit confused by the following statement...
View ArticleCan implementation-defined semantics reference C++ formal mechanisms (like...
This is purely a language-lawyer / abstract-machine specification question. I am fully aware that in portable C++, using volatile for inter-thread synchronization is incorrect and constitutes a data...
View ArticleDo implementation-defined operations with atomic semantics qualify as atomic...
This question is a follow-up to a previous post. Since the previous answers focused primarily on implementation extensions—which was not the core of my question—I have reformulated the problem below...
View ArticleIf A *happens-before* B in an execution, could that execution be produced by...
Consider this example:#include <iostream>#include <mutex>#include <thread>int main(){ std::mutex mtx; int value = 0; int read_t1 = 0; int read_t2 = 0; std::thread t1([&](){...
View ArticleIs there any formal way to distinguish which store operation the current load...
Consider this simple example:#include <thread>#include <atomic>int main(){ std::atomic<int> value = 0; auto t1 = std::jthread([&](){ value.store(1,std::memory_order::release); //...
View ArticleWhy is atomicity needed for the variable counter in this Linux kernel module...
I'm reading this example Linux kernel module from a tutorial, and I do not understand (in this line) why the variable count in struct task_info needs to be atomic_t. The module has a module_init...
View ArticleWhat does constexpr atomic::wait() do at compile time?
What does constexpr void wait(T old, /*...*/) const noexcept; do during constant evaluation, now that it's constexpr in C++26?The description says that it in a loop:Blocks until it is unblocked by an...
View Articlehow to perform atomic read for double?
Why is there no Interlocked.Read function available for double since there are Interlocked.Exchange and Interlocked.CompareExchange methods available for double which can perform more complex functions...
View ArticleDoes thread A seeing one atomic variable loaded with acquire and stored by...
My question boils down to:std::atomic<int> a{0};std::atomic<int> b{0};// thread Aa.store(1, memory_order_relaxed);// thread Bwhile(a.load(memory_order_relaxed) != 1) continue;b.store(2,...
View ArticleHow to build a Main-Worker Group Mutual Exclusion lock using JS Atomics?
I will refer to the main-thread as main. i32a = Int32Array<SharedArrayBuffer>My system includes a SharedArrayBuffer (SAB) created on main, sent over to multiple workers once using...
View ArticleHow do I initialize an array of std::atomics to zeros?
std::array< std::atomic_size_t, 10 > A;// ...std::atomic_init(A, {0}); // errorA = {ATOMIC_VAR_INIT(0)}; // errorHow would you initialize an array of std::atomic to 0s?Even for loops updating one...
View ArticleExclusive Load/Store instructions fail with some MMU configurations on real...
I run into a strange issue (can't explain it myself) when using the exclusive load (ldaxr, ldxr, ...) and store (stxr, ...) instructions on real hardware (Raspberry Pi 3B+ -> Cortex A-53). These...
View ArticleCan C++"happens-before" order contradict physical wall-clock execution time?
Consider the following C++ example:#include <chrono>#include <ctime>#include <iostream>#include <mutex>#include <string>#include <thread>int stock = 10;std::mutex...
View ArticleExclusive load and store instructions require enabled caches on real hardware...
I run into a strange issue (can't explain it myself) when using the exclusive load (ldaxr, ldxr, ...) and store (stxr, ...) instructions on real hardware (Raspberry Pi 3B+ -> Cortex A-53). These...
View ArticlePer-element atomicity of vector load/store and gather/scatter?
Consider an array like atomic<int32_t> shared_array[]. What if you want to SIMD vectorize for(...) sum += shared_array[i].load(memory_order_relaxed)?. Or to search an array for the first non-zero...
View ArticleHow to build a `RW-group mutual exclusion lock` using Atomics
I will refer to the main-thread as main. i32a = Int32Array<SharedArrayBuffer>My system includes a SharedArrayBuffer (SAB) created on main, sent over to multiple workers once using...
View ArticleIs x86 CMPXCHG atomic, if so why does it need LOCK?
The Intel documentation saysThis instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.My question isCan CMPXCHG operate with memory address? From the document...
View ArticleIs fetching std::chrono::steady_clock inside a critical section necessary to...
Consider the following C++ code:#include <iostream>#include <mutex>#include <thread>#include <chrono>#include <string>#include <cassert>int stock = 10;std::mutex...
View ArticleHow to build a shared lock using Atomics
I will refer to the main-thread as main. i32a = Int32Array<SharedArrayBuffer>My system includes a SharedArrayBuffer (SAB) created on main, sent over to multiple workers once using...
View ArticleDo atomics in Java guarantee ordering or only uniqueness?
When executing the following snippet I'm seeing that results are getting properly and uniquely incremented however they are printed out of order (as shown below): import...
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