In lock-free atomic C/C++ programming, can memory reordering affect the...
This title is a bit obscure, but please forgive me for not being able to think of a better way to describe it at the moment.To more clearly articulate my question, I may need to elaborate extensively....
View ArticleIn C++ atomic operations, are the generated values allowed to circularly...
As described in https://cppreference.com/cpp/atomic/memory_order :Even with relaxed memory model, out-of-thin-air values are not allowed to circularly depend on their own computations, for example,...
View ArticleIs a conforming implementation permitted to transform this example to...
Consider this example:#include <atomic>#include <thread>int main(){ std::atomic<int> ack = 1; std::atomic<int> val = 0; std::jthread t1([&]{...
View ArticleHow to implement atomic IO in your own DBMS?
I'm developing my own DBMS (database management system) to get a deep understanding on how this works. My programming language is Java.I have a concept on how to implement locking as well as...
View ArticleHow to atomically modify bits on an IO port on Core M33, which unlike Core M4...
We have compiler for M4 core. Now we want to port it to M33 core which does not support bit banding.we have generated ARM assembly code using below macros which uses bit banding logic.#define...
View ArticleCorrect memory ordering for atomic counter to check association between...
I'm adding a counter to my custom mutex type to track the number of condition variables associated with it. This is for the runtime of a programming language that I'm designing, where a mutex can be...
View ArticleCortex-M33 Exclusive Monitors: Behavior of LDREX/STREX on Internal SRAM vs....
I am working on an ARM Cortex-M33 device and implementing a custom atomic Read-Modify-Write (RMW) bit manipulation routine without native bit-banding support.When compiling my code with optimization...
View ArticleWhat is wrong with this assembly script (wasm) sync barrier using atomics...
I've implemented a sync barrier (note that I also modeled it in a brute force parallel simulator and it finds no invalid state for 3 threads) in assembly script. Here is the barriere code...
View Articlealternative way to have atomic access for peripherals for M33 core
I have LDREX and STREX for SRAM atomic access but does not know how to implement it for peripherals.. Could you please suggest alternative way to implement atomicity on M33 Core for peripherals.
View ArticleClik here to view.
Is correctness of EBR algorithm guaranteed by `seq_cst` also guaranteed by...
Consider this example:#include <atomic>#include <thread>int main(){ std::atomic<int> epoch = {0}; std::atomic<int> value = {1}; std::jthread t1([&](){...
View ArticleIn C++ atomic operations, are the generated values allowed to circularly...
Very similar to In C++ atomic operations, are the generated values allowed to circularly depend on their own computations? but the example used is different (see below).As described in cppreference...
View ArticleAre observable behaviors the same as those when the lock protects the...
Consider this example:#include <atomic>#include <mutex>#include <thread>struct Device { std::atomic<bool> is_associated; std::mutex mutex; void set_associated(bool r) { //...
View ArticleIs the acquire load on top necessary in this C11 Chase-Lev Deque implementation?
I am analyzing the C11 adaptation of the Chase-Lev work-stealing deque from the paper "Correct and Efficient Work-Stealing for Weak Memory Models."The paper says their C11 implementation is "optimal in...
View ArticleClik here to view.
Does the the 2+2W litmus test code in the 'Repairing Sequential Consistency'...
I was reading the paper Repairing Sequential Consistency in C/C++11 by Lahav et al and had a doubt regarding the 2+2W litmus test presented there.Under the section Semantics of SC Atomics in C11, the...
View ArticleIs std::atomic trivially copyable?
The following code prints whether std::atomic<bool> is trivially copyable:#include <atomic>#include <iostream>#include <type_traits>int main(){ std::cout <<...
View ArticleItanium seq_cst Fence and Relaxed Atomics Not Using Plain Loads and Stores
Something I always found strange about the C++ memory model was the fact that, up until C++20, using relaxed atomics and seq_cst fences wasn't equivalent to using seq_cst operations. I assumed this was...
View ArticleDoes the first constraint in [atomics.order] p4 applies to fences?
[atomics.order] p4 saysThere is a single total order S on all memory_order::seq_cst operations, including fences, that satisfies the following constraints. First, if A and B are...
View ArticleDo atomics in Java guarantee ordering or only uniqueness?
When executing the following snippet I'm seeing that results are getting properly and uniquely incremented however they are printed out of order (as shown below): import...
View ArticleIs fetching std::chrono::steady_clock inside a critical section necessary to...
Consider the following C++ code:#include <iostream>#include <mutex>#include <thread>#include <chrono>#include <string>#include <cassert>int stock = 10;std::mutex...
View ArticleIs x86 CMPXCHG atomic, if so why does it need LOCK?
The Intel documentation saysThis instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.My question isCan CMPXCHG operate with memory address? From the document...
View ArticlePer-element atomicity of vector load/store and gather/scatter?
Consider an array like atomic<int32_t> shared_array[]. What if you want to SIMD vectorize for(...) sum += shared_array[i].load(memory_order_relaxed)?. Or to search an array for the first non-zero...
View ArticleCan C++"happens-before" order contradict physical wall-clock execution time?
Consider the following C++ example:#include <chrono>#include <ctime>#include <iostream>#include <mutex>#include <string>#include <thread>int stock = 10;std::mutex...
View ArticleExclusive Load/Store instructions fail with some MMU configurations on real...
I run into a strange issue (can't explain it myself) when using the exclusive load (ldaxr, ldxr, ...) and store (stxr, ...) instructions on real hardware (Raspberry Pi 3B+ -> Cortex A-53). These...
View ArticleHow do I initialize an array of std::atomics to zeros?
std::array< std::atomic_size_t, 10 > A;// ...std::atomic_init(A, {0}); // errorA = {ATOMIC_VAR_INIT(0)}; // errorHow would you initialize an array of std::atomic to 0s?Even for loops updating one...
View ArticleHow to build a Main-Worker Group Mutual Exclusion lock using JS Atomics?
I will refer to the main-thread as main. i32a = Int32Array<SharedArrayBuffer>My system includes a SharedArrayBuffer (SAB) created on main, sent over to multiple workers once using...
View ArticleDoes thread A seeing one atomic variable loaded with acquire and stored by...
My question boils down to:std::atomic<int> a{0};std::atomic<int> b{0};// thread Aa.store(1, memory_order_relaxed);// thread Bwhile(a.load(memory_order_relaxed) != 1) continue;b.store(2,...
View Articlehow to perform atomic read for double?
Why is there no Interlocked.Read function available for double since there are Interlocked.Exchange and Interlocked.CompareExchange methods available for double which can perform more complex functions...
View ArticleWhat does constexpr atomic::wait() do at compile time?
What does constexpr void wait(T old, /*...*/) const noexcept; do during constant evaluation, now that it's constexpr in C++26?The description says that it in a loop:Blocks until it is unblocked by an...
View ArticleWhy is atomicity needed for the variable counter in this Linux kernel module...
I'm reading this example Linux kernel module from a tutorial, and I do not understand (in this line) why the variable count in struct task_info needs to be atomic_t. The module has a module_init...
View ArticleIs there any formal way to distinguish which store operation the current load...
Consider this simple example:#include <thread>#include <atomic>int main(){ std::atomic<int> value = 0; auto t1 = std::jthread([&](){ value.store(1,std::memory_order::release); //...
View Article
![Personal Investments • Re: 401k investments [which to choose?]](http://i.imgur.com/wA51OIw.png)
